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Integrated Circuit Systems, Inc.
ICS9250-25
Preliminary Product Preview
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: 810/810E and Solano type chipset Output Features: * 2 - CPUs @ 2.5V, up to 153.33MHz. * 13 - SDRAM @ 3.3V, up to 153.33MHz. * 3 - 3V66 @ 3.3V, 2x PCI MHz. * 8 - PCI @3.3V. * 1 - 48MHz, @3.3V fixed. * 1 - 24MHz @ 3.3V * 1 - REF @3.3V, 14.318MHz. Features: * Up to 153.33MHz frequency support * Support power management through PD#. * Spread spectrum for EMI control ( 0.25%) center spread. * Uses external 14.318MHz crystal * FS pins for frequency select Key Specifications: * CPU Output Jitter: <250ps * IOAPIC Output Jitter: <500ps * 48MHz, 3V66, PCI Output Jitter: <500ps * Ref Output Jitter. <1000ps * CPU Output Skew: <175ps * PCI Output Skew: <500ps * 3V66 Output Skew <175ps * For group skew timing, please refer to the Group Timing Relationship Table.
VDDREF X1 X2 GNDREF GND3V66 3V66-0 3V66-1 3V66-2 VDD3V66 VDDPCI 1 *FS0/PCICLK0 1 *FS1/PCICLK1 PCICLK2 GNDPCI PCICLK3 PCICLK4 PCICLK5 VDDPCI PCICLK6 PCICLK7 GNDPCI PD# SCLK SDATA VDDSDR SDRAM11 SDRAM10 GNDSDR
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 REF0/FS4* VDDLAPIC IOAPIC VDDLCPU CPUCLK0 CPUCLK1 GNDLCPU GNDSDR SDRAM0 SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 SDRAM5 GNDSDR SDRAM6 SDRAM7 SDRAM_F VDDSDR GND48 24MHz/FS2* 1 48MHz/FS3* VDD48 VDDSDR SDRAM8 SDRAM9 GNDSDR
1
56-Pin 300 mil SSOP
1. These pins will have 1.5 to 2X drive strength. * 120K ohm pull-up to VDD on indicated inputs.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24MHz
ICS9250-25
REF0
CPU DIVDER
2
CPUCLK [1:0]
SDRAM DIVDER
12
SDRAM [11:0] SDRAM_F
FS[4:0] PD#
Control Logic Config.
IOAPIC DIVDER
IOAPIC
SDATA SCLK
Reg.
PCI DIVDER
8
PCICLK [7:0]
3V66 DIVDER
3
3V66 [2:0]
9250-25 Rev A 10/03/00 Third party brands and names are the property of their respective owners.
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.
ICS9250-25
Preliminary Product Preview
General Description
The ICS9250-25 is a single chip clock solution for desktop designs using the 810/810E and Solano style chipset. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9250-25 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection.
Pin Configuration
PIN P I N NA M E NUMBER 1, 9, 10, 18, 25, VDD 32, 33, 37, 45 2 3 4, 5, 14, 21, 28, 29, 36, 41, 49 8, 7, 6 11 12 20, 19, 17, 16, 15, 13 22 23 24 34 X1 X2 GND 3V66 [2:0] PCICLK01 FS0 PCICLK11 FS1 PCICLK [7:2] PD# SCLK SDATA 48MHz FS3 FS2 24MHz SDRAM_F SDRAM [11:0] GNDL CPUCLK [1:0] VDDL IOAPIC FS4 REF01 TYPE PWR IN OUT PWR OUT OUT IN IN IN OUT IN IN IN OUT IN IN OUT OUT OUT PWR OUT PWR OUT IN OUT 3.3V power supply Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Ground pins for 3.3V supply 3 . 3 V F i xe d 6 6 M H z c l o c k o u t p u t s f o r H U B 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs, with Synchronous CPUCLKS Logic input frequency select bit. Input latched at power on. 3.3V PCI clock outputs, with Synchronous CPUCLKS Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Clock input of I2C input Data input for I2C serial input. 3 . 3 V F i xe d 4 8 M H z c l o c k o u t p u t f o r U S B Logic input frequency select bit. Input latched at power on. Logic input frequency select bit. Input latched at power on. 3.3V fixed 24MHz output 3.3V free running 100MHz SDRAM not affected by I2C 3.3V output running 100MHz. All SDRAM outputs can be turned off t h r o u g h I 2C Ground for 2.5V power supply for CPU & APIC 2.5V Host bus clock output. Output frequency derived from FS pins. 2.5V power suypply for CPU, IOAPIC 2.5V clock outputs running at 16.67MHz. Logic input frequency select bit. Input latched at power on. 3.3V, 14.318MHz reference clock output. DESCRIPTION
35 38 48, 47, 44, 43, 42, 40, 39, 31, 30, 30, 27, 26 50 51, 52 53, 55 54 56
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2
ICS9250-25
Preliminary Product Preview
Frequency Selection
FS4
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
FS3
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
CPU MHz
55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 83.30 90.00 100.30 103.00 112.50 115.00 120.00 125.00 128.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 125.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33
SDRAM MHz
82.50 90.00 100.20 102.50 105.00 108.00 112.50 115.50 83.30 90.00 100.30 103.00 112.50 115.00 120.00 125.00 128.00 130.00 133.70 137.00 140.00 145.00 150.00 153.33 93.75 97.50 100.28 102.75 105.00 108.75 112.50 115.00
3V66 MHz
55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 55.53 60.00 66.87 68.67 75.00 76.67 80.00 83.33 64.00 65.00 66.85 68.50 70.00 72.50 75.00 76.67 62.50 65.00 66.85 68.50 70.00 72.50 75.00 76.67
PCI MHz
27.5 30 33.4 34.165 35 36 37.5 38.5 27.8 30.0 33.4 34.3 37.5 38.3 40.0 41.7 32.0 32.5 33.4 34.3 35.0 36.3 37.5 38.3 31.3 32.5 33.4 34.3 35.0 36.3 37.5 38.3
IOAPIC MHz
13.75 15 16.7 17.0825 17.5 18 18.75 19.25 13.9 15.0 16.7 17.2 18.8 19.2 20.0 20.8 16.0 16.3 16.7 17.1 17.5 18.1 18.8 19.2 15.6 16.3 16.7 17.1 17.5 18.1 18.8 19.2
Clock Enable Configuration
PD# 0 1 CPUCLK LOW ON SDRAM LOW ON IOAPIC LOW ON 66MHz LOW ON PCICLK LOW ON REF, 48MHz LOW ON Osc OFF ON VCOs OFF ON
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3
ICS9250-25
Preliminary Product Preview
Byte 0: Functionality and frequency select register (Default=0) (1 = enable, 0 = disable)
Bit Bit (2,7:4)
Description CPUCLK SDRAM MHz MHz 0 0 0 0 0 55.00 82.50 0 0 0 0 1 60.00 90.00 0 0 0 1 0 66.80 100.20 0 0 0 1 1 68.33 102.50 0 0 1 0 0 70.00 105.00 0 0 1 0 1 72.00 108.00 0 0 1 1 0 75.00 112.50 0 0 1 1 1 77.00 115.50 0 1 0 0 0 83.30 83.30 0 1 0 0 1 90.00 90.00 0 1 0 1 0 100.30 100.30 0 1 0 1 1 103.00 103.00 0 1 1 0 0 112.50 112.50 0 1 1 0 1 115.00 115.00 0 1 1 1 0 120.00 120.00 0 1 1 1 1 125.00 125.00 1 0 0 0 0 128.00 128.00 1 0 0 0 1 130.00 130.00 1 0 0 1 0 133.70 133.70 1 0 0 1 1 137.00 137.00 1 0 1 0 0 140.00 140.00 1 0 1 0 1 145.00 145.00 1 0 1 1 0 150.00 150.00 1 0 1 1 1 153.33 153.33 1 1 0 0 0 125.00 93.75 1 1 0 0 1 130.00 97.50 1 1 0 1 0 133.70 100.28 1 1 0 1 1 137.00 102.75 1 1 1 0 0 140.00 105.00 1 1 1 0 1 145.00 108.75 1 1 1 1 0 150.00 112.50 1 1 1 1 1 153.33 115.00 0-Frequency is selected by hardware select, latched inputs 1- Frequency is selected by Bit 2,6:4 0- Normal 1- Spread spectrum enable 0.25% Center Spread 0- Running 1- Tristate all outputs 3V66 MHz 55.00 60.00 66.80 68.33 70.00 72.00 75.00 77.00 55.53 60.00 66.87 68.67 75.00 76.67 80.00 83.33 64.00 65.00 66.85 68.50 70.00 72.50 75.00 76.67 62.50 65.00 66.85 68.50 70.00 72.50 75.00 76.67 PCICLK 27.5 30 33.4 34.165 35 36 37.5 38.5 27.8 30.0 33.4 34.3 37.5 38.3 40.0 41.7 32.0 32.5 33.4 34.3 35.0 36.3 37.5 38.3 31.3 32.5 33.4 34.3 35.0 36.3 37.5 38.3 IOAPIC MHz 13.75 15 16.7 17.0825 17.5 18 18.75 19.25 13.9 15.0 16.7 17.2 18.8 19.2 20.0 20.8 16.0 16.3 16.7 17.1 17.5 18.1 18.8 19.2 15.6 16.3 16.7 17.1 17.5 18.1 18.8 19.2
PWD
Bit (2, 7:4)
00001 Note 1
Bit 3 Bit 1 Bit 0
0 1 0
Notes: 1. Default at power-up will be for latched logic inputs to define frequency, as displayed by Bit 3.
2. The I2C readback for Bit 2, 7:4 indicate the revision code.
4
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ICS9250-25
Preliminary Product Preview
Byte 1: Control Register (1 = enable, 0 = disable)
Byte 2: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 35 34 38
PWD X X X 1 1 1 1 1
Description FS3# FS0# FS2# 24MHz (Reserved) 48MHz (Reserved) SDRAM_F
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 39 40 42 43 44 46 47 48
PWD 1 1 1 1 1
1
1 1
Description SDRAM7 SDRAM6 SDRAM5 SDRAM4 SDRAM3 SDRAM2 SDRAM1 SDRAM0
Byte 3: Control Register (1 = enable, 0 = disable)
Byte 4: Control Register (1 = enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 20 19 17 16 15 13 12 11
PWD 1 1 1 1 1
1
1 1
Description PCICLK7 PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 8 6 7 54 51 52
PWD 1 1 1 X 1 X 1 1
Description 3V66_2 3V66_0 3V66_1 FS4# IOAPIC FS1# CPUCLK1 CPUCLK0
Byte 5: Control Register (1 = enable, 0 = disable)
Byte 6: Peripheral , Active/Inactive Register (1= enable, 0 = disable)
Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Pin# 26 27 30 31
PWD 1 1 1 1 1 1 1 1
Description (Reserved) (Reserved) (Reserved) (Reserved) SDRAM11 SDRAM10 SDRAM9 SDRAM8
Bit Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Pin# -
PWD 0 0 0 0 0 1 1 0
Description R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e ) R e s e r ve d ( N o t e )
Note: Dont write into this register, writing into this register can cause malfunction
Notes: 1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be configured during the normal modes of operation. 2. PWD = Power on Default
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5
ICS9250-25
Preliminary Product Preview
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 V 3.6V GND 0.5 V to V DD +0.5 V 0C to +70C 65C to +150C 115C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Group Timing Relationship Table1
Group CPU 66MHz SDRAM 100MHz Offset CPU to SDRAM CPU to 3V66 SDRAM to 3V66 3V66 to PCI PCI to PCI USB & DOT 2.5ns 7.5ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 100MHz SDRAM 100MHz Offset 5.0ns 5.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz SDRAM 100MHz Offset 0.0ns 0.0ns 0.0ns 1.5-3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A CPU 133MHz SDRAM 133MHz Offset 3.75ns 0.0ns 3.75ns 1.5 -3.5ns 0.0ns Asynch Tolerance 500ps 500ps 500ps 500ps 1.0ns N/A
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +5%, VDDL=2.5 V+ 5%(unless otherwise stated) PARAMETER Input High Voltage Input Low Voltage Input High Current Input Low Current Input Low Current Operating Supply Current Power Down Supply Current Input frequency Pin Inductance Input Capacitance1 SYMBOL VIH VIL IIH IIL1 IIL2 IDD3.3OP IDD3.3PD Fi Lpin CIN Cout CINX Ttrans Ts
1
CONDITIONS
VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors CL = 0 pF; Select @ 66M CL = 0 pF; With input address to Vdd or GND VDD = 3.3 V; Logic Inputs Out put pin capacitance X1 & X2 pins To 1st crossing of target Freq. From 1st crossing to 1% target Freq. From VDD = 3.3 V to 1% target Freq. output enable delay (all outputs) output disable delay (all outputs)
MIN 2 VSS-0.3 -5 -5 -200
TYP
MAX UNITS VDD+0.3 V 0.8 V A 5 A A 100 600 mA A MHz nH pF pF pF mS mS mS nS nS
14.318 7 5 6 45 3 3 1 1 3 10 10
27
Transition Time1 Settling Time1 Clk Stabilization Delay
1
TSTAB t PZH,tPZH t PLZ,t PZH
Guarenteed by design, not 100% tested in production.
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6
ICS9250-25
Preliminary Product Preview
Electrical Characteristics - CPU
TA = 0 - 70C, VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP2B1 RDSN2B1 VOH2B VOL2B IOH2B IOL2B tr2B1 tf2B1 dt2B1 tsk2B1 tjcyc-cyc1 VO = VDD*(0.5)
CONDITIONS VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 1.0V , VOH@ MAX= 2.375V VOL @MIN= 1.2V , VOL@ MAX= 0.3V VOL = 0.4 V, VOH = 2.0 V VOH = 0.4 V, VOL = 2.0 V VT = 1.25 V VT = 1.25 V VT = 1.25 V
MIN 13.5 13.5 2 -27 27 0.4 0.4 45
TYP
MAX UNITS 45 45 0.4 -27 30 1.6 1.6 V V mA mA ns ns ns ps ps
50
55 175 250
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 3V66
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1 1 1 1
CONDITIONS VO = VDD*(0.5)
MIN 12
TYP
MAX UNITS 55 55 0.55 -33 38 1.6 1.6 55 175 500 V V mA mA ns ns % ps ps
VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 0.4 0.4 45
dt1
tsk1 tjcyc-cyc
Guarenteed by design, not 100% tested in production.
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7
ICS9250-25
Preliminary Product Preview
Electrical Characteristics - IOAPIC
TA = 0 - 70C;VDDL = 2.5 V +/-5%; CL = 10 - 20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP4B1 RDSN4B1 VOH4\B VOL4B IOH4B IOL4B tr4B1 tf4B1 dt4B1 tjcyc-cyc VO = VDD*(0.5)
CONDITIONS VO = VDD*(0.5) IOH = -5.5 mA IOL = 9.0 mA VOH@ min = 1.4 V, VOH@ MAX = 2.5 V VOL@ MIN = 1.0 V, VOL@ MAX= 0.2 VOL = 0.4 V, VOH = 2.0 V VOH = 2.0 V, VOL = 0.4 V VT = 1.25 V VT = 1.25 V
MIN 9 9 2 -36 36 0.4 0.4 45
TYP
MAX UNITS 30 30 0.4 -21 31 1.6 1.6 55 500 V V mA mA nS nS % pS
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - SDRAM
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 20 - 30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP3 RDSN3 VOH3 VOL3 IOH3 IOL3 Tr31 Tf3 Dt3
1 1 1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA VOH @MIN= 2.0 V, VOH@ MAX=3.135 V VOL@ MIN= 1.0 V, VOL@ MAX=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 10 10 2.4 -54 54 0.4 0.4 45
TYP
MAX UNITS 24 24 0.4 -46 53 1.6 1.6 55 250 250 V V mA mA ns ns % ps ps
Tsk3 tj cyc-cyc
Guarenteed by design, not 100% tested in production.
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ICS9250-25
Preliminary Product Preview
Electrical Characteristics - PCI
TA = 0 - 70C; VDD = 3.3 V +/-5%; CL = 10-30 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Skew Jitter
1
SYMBOL RDSP1 RDSN1 VOH1 VOL1 IOH1 IOL1 tr11 tf1
1 1 1 1 1
CONDITIONS VO = VDD*(0.5)
MIN 12
TYP
MAX UNITS 55 55 0.55 -33 38 2 2 55 500 500 V V mA mA ns ns % ps ps
VO = VDD*(0.5) 12 IOH = -1 mA 2.4 IOL = 1 mA VOH@ MIN = 1.0 V, VOH@ MAX = 3.135 V -33 VOL@ MIN = 1.95 V, VOL@ MAX= 0.4 30 VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V 0.5 0.5 45
dt1
tsk1 tjcyc-cyc
Guarenteed by design, not 100% tested in production.
Electrical Characteristics - 48M, REF
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-5%; CL = 10 -20 pF (unless otherwise stated) PARAMETER Output Impedance Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time Fall Time Duty Cycle Jitter
1
SYMBOL RDSP5 RDSN5 VOH5 VOL5 IOH5 IOL5 tr5 1 tf5
1 1 1
CONDITIONS VO = VDD*(0.5) VO = VDD*(0.5) IOH = 1 mA IOL = -1 mA VOH @MIN=1 V, VOH@MAX= 3.135 V VOL@MIN=1.95 V, VOL@MIN=0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V
MIN 20 20 2.4 -29 29
TYP
MAX UNITS 60 60 0.4 -23 27
V V mA mA
nS nS % pS pS
1.8 1.7 45
4 4 55 500 1000
dt5 1 tjcyc-cyc tjcyc-cyc1
1
VT = 1.5 V; Fixed Clocks VT = 1.5 V; Ref Clocks
Guarenteed by design, not 100% tested in production.
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9
ICS9250-25
Preliminary Product Preview General I2C serial interface information
The information in this section assumes familiarity with I2C programming. For more information, contact ICS for an I2C programming application note.
How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending first byte (Byte 0) through byte 5 ICS clock will acknowledge each byte one at a time. Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends first byte (Byte 0) through byte 5 Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
How to Write:
Controller (Host) Start Bit Address D2(H) Dummy Command Code ACK Dummy Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Stop Bit
ACK Stop Bit ACK Byte 5 ACK Byte 4 ACK Byte 3 ACK Byte 2 ACK Byte 1 ACK Byte 0
ICS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
ACK
ACK Byte Count
Notes:
1. 2. 3. 4. 5. The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for verification. Read-Back will support Intel PIIX4 "Block-Read" protocol. The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode) The input is operating at 3.3V logic levels. The data byte format is 8 bit bytes. To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes. The data is loaded until a Stop sequence is issued. At power-on, all registers are set to a default condition, as shown.
6.
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ICS9250-25
Preliminary Product Preview
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS9250-25 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5bit internal data latch. At the end of Power-On reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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11
ICS9250-25
Preliminary Product Preview
Power Down Waveform
1. After PD# is sampled active (Low) for 2 consective rising edges of CPUCLKs, all the output clocks are driven Low on their next High to Low tranistiion. 2. Power-up latency <3ms. 3. Waveform shown for 100MHz
Note
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12
ICS9250-25
Preliminary Product Preview
0ns
10ns
20ns
30ns
40ns
Cycle Repeats
CPU 66MHz CPU 100MHz CPU 133MHz
SDRAM 100MHz SDRAM 133MHz
3.5V 66MHz PCI 33MHz APIC 33MHz REF 14.318MHz USB 48MHz
Group Offset Waveforms
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13
ICS9250-25
Preliminary Product Preview
SYMBOL
In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX 2.413 0.203 0.203 2.794 0.406 0.343 .095 .008 .008 .110 .016 .0135
A A1 b c D E E1 e h L N VARIATIONS N 56
0.127 0.254 SEE VARIATIONS 10.033 7.391 0.381 10.668 7.595 0.635
.005 .010 SEE VARIATIONS .395 .291 .015 .420 .299 .025
0.635 BASIC 0.508 1.016 SEE VARIATIONS 0 8
0.025 BASIC .020 .040 SEE VARIATIONS 0 8
D mm. MIN 18.288 MAX 18.542 MIN .720
D (inch) MAX .730
6/1/00 REV B
JEDEC MO-118 DOC# 10-0034
Ordering Information
ICS9250yF-25-T
Example:
ICS XXXX y F - PPP - T
Designation for tape and reel packaging Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type F=SSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV = Standard Device
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14
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to change without notice.

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